1. Technical Field
The present invention relates generally to delay locked loops and, more particularly, to an improved delay locked loop for synchronizing a system clock with data lines of a semiconductor device.
2. Related Art
Clock frequency requirements of semiconductor devices are continually increasing. This is especially true, for example, for devices such as Double Data Rate (DDR) synchronous dynamic random access memory (SDRAMs). It is important to minimize on-chip clock distribution delay and total system clock skew in order to ensure accurate data communication with a semiconductor device. For this reason, semiconductor devices typically include delay locked loops (DLLs). A DLL facilitates canceling on-chip amplification and buffering delays and thereby improves data input and output timing margins.
In a DLL feedback loop, on-chip delay is often modeled. The modeled delay approximates the actual delay caused by a semiconductor device""s circuit components, such as: a receiver, a driver and an off chip driver (OCD), as well as that caused by an external termination and load. A delay model often utilizes an inverter chain to account for delay. In order to accurately align the phase of the DQs with an incoming clock signal, VCLK, it is important to accurately model the delay. One design for a DLL that models on-chip delays is disclosed in U.S. Pat. No. 5,355,037 issued to Andresen, et al., herein incorporated by reference.
Some early DLL feedback loop designs suffered from inaccurate modeling of the actual delay caused by the circuit components. These inaccuracies resulted from variations in technology and unaccounted for temperature effects. Furthermore, these early designs poorly modeled delay caused by chip packaging components, such as bond wire and lead inductance and capacitance, as well as the module-to-board interface (e.g., Stub Series Terminated Logic (SSTL)).
In U.S. Pat. No. 6,137,327 issued to Schnell, herein incorporated by reference, a DLL circuit 100 is disclosed that more accurately models delays, as shown in FIG. 1. The DLL circuit 100 includes: a first receiver 102, a phase detector 104, delay control circuit and delay line elements 106, a DLL clock driver 108, a plurality of OCDs 110, a plurality of pads 114, an OCD mimic circuit 112, SSTL interface logic circuit 116, a second receiver 118, and a delay circuit 120.
The first receiver 102 receives a system clock signal 150 and provides a reference clock signal 152. The phase detector 104 receives the first clock signal 152, compares it to a feedback clock signal 168, and generates control signals 156 for the delay control circuit and delay line elements 106. The delay control circuit and delay line elements 106 delay reference clock signal 152 by a desired amount. The DLL clock driver 108 supplies a DLL clock signal 160 to the plurality of off-chip drivers (OCDs) 110 and also to the OCD mimic circuit 112. The OCD mimic circuit 112 provides an FB_IFCLK signal 164 through SSTL interface logic 116 to the second receiver 118. The second receiver 118 provides an amplified (and delayed) clock signal 166 to the delay circuit 120. The delay circuit 120 is a resistor-capacitor (RC) delay element, or a delay inverter chain, or both. The delay circuit 120 mimics inductance, capacitance and resistance (LRC) aspects of the chip packaging. The delay circuit 120 provides the feedback clock signal 168 to the phase detector 104.
The feedback loop disclosed by Schnell does show some improvements over earlier designs. However, delays caused by the package and the external loads are still modeled by delay elements. Furthermore, the delay is set to a fixed value for all operations and loads. It would be desirable to have a DLL circuit that accounts for the effective load of the OCDs. It also would be desirable to have a DLL circuit that does not require modeling for delay calculations.
A DLL for a semiconductor device may include a phase detector that receives a reference clock signal and a feedback clock signal and provides, as a function of the reference clock signal and the feedback clock signal, a delay control signal. The DLL may also include a delay circuit in communication with the phase detector, wherein the delay circuit receives the reference clock signal and the delay control signal and provides, as a function of the reference clock signal and the delay control signal, a delayed clock signal. The DLL may further include an OCD in communication with the delay circuit, wherein the OCD receives the delayed clock signal and provides, as a function of the delayed clock signal, an interim feedback clock signal. The DLL may also include a receiver in communication with the phase detector and the OCD, wherein the receiver receives the interim feedback clock signal and provides, as a function of the interim feedback clock signal, the feedback clock signal.
The DLL may include a first pad coupled to the receiver and a second pad coupled to the OCD, wherein the receiver and the OCD communicate via the first pad and the second pad. The DLL may also include a switch coupled between the receiver and the OCD, wherein the switch selectively enables communication between the receiver and the OCD. The DLL may further include an input selection switch having a first input, a second input, and an output, wherein the first input is in communication with the delay circuit and receives the delayed clock signal, the second input receives a data output signal, and the output is in communication with the OCD and selectively provides the delayed clock signal to the OCD.
Furthermore, the DLL may also include an output selection switch having an input, a first output, and a second output, wherein the input is in communication with the receiver circuit, the first output is in communication with a data input line, and the second output is in communication with the phase detector and selectively provides the feedback clock signal to the OCD. The DLL may also include a clock receiver coupled to the phase detector and the delay circuit, wherein the clock receiver receives a system clock signal and provides, as a function of the system clock signal, the reference clock signal.
A DLL for a semiconductor device may include a phase detector, wherein the phase detector receives a reference clock signal and a feedback clock signal and provides, as a function of the reference clock signal and the feedback clock signal, a delay control signal. The DLL may additionally include a latch in communication with the phase detector, wherein the latch receives the delay control signal and a command signal and provides a latched delay control signal. The DLL may also include a delay circuit in communication with the latch, wherein the delay circuit receives the reference clock signal and the latched delay control signal and provides, as a function of the reference clock signal and the latched delay control signal, a delayed clock signal. The delay circuit may include a plurality of delay elements. The DLL may also include an OCD in communication with the delay circuit, wherein the OCD receives the delayed clock signal and provides, as a function of the delayed clock signal, an interim feedback clock signal. The OCD may include a plurality of OCDs.
The DLL may also include a receiver in communication with the OCD and the phase detector, wherein the receiver receives the interim feedback clock signal and provides, as a function of the interim feedback clock signal, the feedback clock signal. The DLL may also include a first pad coupled to the receiver and a second pad coupled the OCD, wherein the receiver and the OCD communicate via the first pad and the second pad. The DLL may additonally include a switch coupled between the receiver and the OCD, wherein the switch receives the command signal and selectively enables communication between the receiver and the OCD in response to the command signal.
The DLL may further include an input selection switch having a first input, a second input, and an output, wherein the input selection switch receives the command signal, the first input is in communication with the delay circuit and receives the delayed clock signal, the second input receives a data output signal, and the output is in communication with the OCD and selectively provides the delayed clock signal to the OCD in response to the command signal. The DLL may also include an output selection switch having an input, a first output, and a second output, wherein the output selection switch receives the command signal, the input is in communication with the receiver circuit, the first output is in communication with a data input line, and the second output is in communication with the phase detector and selectively provides the feedback clock signal to the OCD in response to the command signal.
Furthermore, the DLL may include a receiver coupled to the phase detector and the delay circuit, wherein the receiver receives a system clock signal and provides, as a function of the system clock signal, the reference clock signal. The DLL may also include a clock driver, wherein the clock driver is in communication with the delay circuit and provides the delayed clock signal to OCD.
A method for locking a delay loop for a semiconductor device may include receiving a reference clock signal and a feedback clock signal with a phase detector. The method may also include providing a delay control signal that is a function of the reference clock signal and the feedback clock signal with the phase detector. The method may further include receiving the delay control signal with a delay circuit. The method may also include providing a delayed clock signal that is a function of the reference clock signal and the delay control signal with the delay circuit. The method may further include receiving the delayed clock signal with an OCD and providing an interim feedback clock signal that is a function of the delayed clock signal via the OCD. The method may also include receiving the interim feedback clock signal with a receiver, and providing the feedback clock signal to the phase detector via the receiver, wherein the feedback clock signal is a function of the interim feedback clock signal.
The method may also include providing an update command signal. Furthermore, receiving the delay control signal with a delay circuit may include receiving the delay control signal with a latch and latching the delay control signal in response to the update command signal. Alternatively, receiving the delayed clock signal with an OCD may include switching between receiving the delayed clock signal and receiving a data output signal in response to the update command signal. As another alternative, receiving the interim feedback clock signal with a receiver may include switching between receiving the interim feedback clock signal and receiving a data input signal in response to the command signal. As a further alternative, providing the feedback clock signal to the phase detector via the receiver may include switching between providing the feedback clock signal and providing a data input signal in response to the update command signal.